In order to convey high-frequency signals, a so-called microstrip technology implemented on a printed circuit is, for example, used. Printed conductive tracks are produced on faces of the printed circuit. These faces may be external or internal and may be separated by one or more conductive planes. The microstrip lines have particular dimensions so that, once associated with the conductive planes, they form impedance-matched lines. This matching makes it possible to ensure a certain transparency of the line with regard to the signal conveyed. In other words, the aim is to minimize the electrical power losses of the signal along the line.
The transmission line may have to change from one face to another of the printed circuit. For this, vias, also known as metallized holes, are used that ensure electrical contact between the tracks of different faces. The vias are generally of circular section. The simplest way of producing these vias is drilling of the printed circuit followed by metallization of the interior of the hole.
FIG. 1 illustrates this embodiment in a printed circuit 10 comprising two external faces 11 and 12 each bearing a microstrip line, respectively 13 and 14. The two lines 13 and 14 are interconnected by means of a via 15. FIG. 2 represents an enlarged view of the printed circuit 10 around the via 15 and FIG. 3 represents the printed circuit 10 in cross section around the via 15. The printed circuit also comprises two conductive planes 16 and 17. Around the via 15, the two conductive planes 16 and 17 are interrupted to form, in each, a resist, respectively 18 and 19, through which the via 15 passes.
A simple radio frequency interconnect via in a multilayer structure, as illustrated in FIGS. 1 to 3, exhibit spurious electrical effects, which in particular break the transparency of the via with regard to the signal conveyed. This transparency is above all degraded at high frequency. These effects, notably linked to the intrinsic inductive nature of the via 15, then result in a mismatching and greater or lesser insertion losses on the signal.
FIG. 4 represents the matching level S11 of the example represented in FIGS. 1 to 3 expressed in dB according to the frequency of the signal conveyed by the interconnect. The matching level illustrates the electrical power reflected by the interconnect. Still for this example, FIG. 5 represents the insertion level S21 or insertion loss expressed in dB according to the frequency of the signal. The insertion level illustrates the electrical power loss in transmission at the interconnect.
It is, in this case, found that the via 15 exhibits a matching level of −14.5 dB for the useful working frequency of 9.3 GHz, and insertion losses of 0.49 dB for this same frequency. Given these results, the interconnect is far from optimal.